1. Field of the Invention
The present invention relates to an integrated circuit, more particularly, to a testing technique for variable delay circuits within an integrated circuit.
2. Description of the Related Art
Recently, performances of CPUs and memories have been increasingly improved, and the operating speeds of interfaces of the CPUs and memories have been enhanced accordingly. The enhancement of the operating speeds of the CPU and memory interfaces requires incorporating variable delay circuits within integrated circuits to provide delay adjustments of data buses connected among flipflops and system clocks fed to flipflops. The variable delay circuits allow offering sufficient setup times and hold times to flipflops within an integrated circuit in the high frequency operation.
Further operation speed enhancement in future requires minute adjustment of variable delay circuits. This undesirably makes it difficult to detect failures in the integrated circuit.
In and after the manufacture process of an integrated circuit, integrated circuits are tested to find failures therein. It is desirable for improving testability that all the circuits integrated can be tested by a built-in test technique.
In connection with a testing technique for variable delay circuits, Japanese Laid-Open Patent Application No. JP-A 2004-139718 discloses an output driver which is configured to adjust the delay thereof. This output driver includes an output terminal, a pull-up driver, a pull-down driver, and a mode register set. The pull-up driver pulls up the output terminal, while the pull-down driver pulls down the output terminal. The mode register set contains CAS (Column Address Strobe) latency information of the semiconductor memory. The output driver is adapted to adjust the drive capabilities of the pull-up and pull-down drivers in response to the CAS latency information.
FIGS. 1A and 1B are circuit diagrams illustrating the configuration of the output driver, denoted by the numeral 20, disclosed in this patent application. FIG. 1A shows the configuration of the output driver 20, and FIG. 2B shows the configuration of a controller circuitry connected to the output driver 20.
The output driver 20 is provided with a pull-up driver 23, a pull-down driver 24, an input terminal DQOUT and an output terminal DQ. The pull-up driver 23 includes a set of PMOS switch transistors P14 to P17 and a set of pull-up transistors P10 to P13. The pull-down driver 24 includes a set of NMOS switch transistors N14 to N17 and a set of pull-down transistors N10 to N13.
The control circuit 22 has a plurality of CAS latency inputs connected with a mode register set 21. The CAS latency inputs are denoted by the symbols CL1.5, CL2.0, CL2.5, and CL3.0, and associated with different CAS latencies of 1.5, 2.0, 2.5, and 3.0 clock cycles, respectively. One of the CAS latency inputs CL1.5, CL 2.0, CL2.5, and CL3.0 of the control circuit 22 is activated in response to the selection of the CAS latencies.
The control circuit 22 feeds drive capability control signals a0 to a3 to the gates of the pull-down transistors N10 to N13, respectively. The control signals a0 to a3 are also fed to the inverters 25 to 28. The inverters 25 to 28 generate inversed drive capability control signals ab0 to ab3 in response to the drive capability control signals a0 to a3, respectively.
The pull-up transistors P10 to P13 have sources connected to a power supply line VDD and drains connected to the sources of the PMOS switch transistors P14 to P17, respectively. In addition, the pull-up transistors P10 to P13 receive the inversed drive capability control signals ab0 to ab3 on the gates thereof, respectively. The PMOS switch transistors P14 to P17 have gates commonly connected to the input terminal DQOUT, and drains commonly connected to the output terminal DQ.
Correspondingly, the pull-down transistors N10 to N13 have sources connected to a ground line VSS and drains connected to the sources of the NMOS switch transistors N14 to N17, respectively. In addition, the pull-down transistors N10 to N13 receive the drive capability control signals a0 to a3 on the gates thereof, respectively. The NMOS switch transistors N14 to N17 have gates commonly connected to the input terminal DQOUT, and drains commonly connected to the output terminal DQ.
The pull-up transistors P10 to P13 are selectively enabled in response to the input signal received from the input terminal DQOUT and the inversed drive capability control signals ab0 to ab3, respectively. Correspondingly, the pull-down transistors N10 to N13 are selectively enabled in response to the input signal received from the input terminal DQOUT and the drive capability control, signals a0 to a3, respectively.
The pull-up driver 23 thus designed is used to pull up the output terminal DQ, and the pull-down driver 24 thus designed is used to pull down the output terminal DQ.
The mode register set 21 stores therein CAS latency information indicative of the CAS latency, and selectively activates one of the CAS latency inputs CL1.5, CL 2.0, CL2.5, and CL3.0 of the control circuit 22 in response to the stored CAS latency information.
The drive capabilities of the pull-up driver 23 and the pull-down driver 24 are adjusted in response to the CAS latency information stored in the mode register set 21. More specifically, the control circuit 22 outputs the drive capability control signals a0 to a3 in response to which of the CAS latency inputs CL information stored in the mode register set 21, and the inverters 25 to 28 outputs the inversed drive capability control signals ab0 to ab3 accordingly. The logic values of the inversed drive capability control signals ab0 to ab3 are complementary to those of the drive capability control signals a0 to a3. The drive abilities of the pull-up driver 23 and pull-down driver 24 shown in FIG. 1A are controlled in response to the control signals a0 to a3 and ab0 to ab3.
One common approach for detecting a failure in the output driver is to measure changes in the current on the output terminal DQ.
Recently, enhancement of the signal interfacing speed of the system has been strongly desired, and this requires latching data on a data bus within the integrated circuit with a high frequency system clock.
The use of the high frequency system clock makes it difficult to assure sufficient setup times and hold times for respective flipflops due to undesired delay variations in the clock distribution system and data bus. In order to address this problem, variable delay circuits are integrated within the semiconductor integrated circuit to assure sufficient setup times and hold times for respective flipflops within the integrated circuit.
One approach for achieve minute delay adjustment of the clock distribution system and data bus may be to incorporate the circuit shown in FIG. 1A within the clock distribution system and data bus; however, this approach is not preferable in terms of testability. Variable delay circuits which adjust delays of data signals and clock signals exchanged between flipflops within the integrated circuit are not directly connected to external output pads. This implies that changes in the currents in the case of failure cannot be detected. When the output driver 20 shown in FIG. 1A is integrated within the internal circuit of a semiconductor integrated circuit, the failure of the output driver 20 cannot be detected.
One approach for addressing the problem of the failure detection may be to incorporate a built-in test circuit. FIGS. 2A and 2B show an exemplary configuration of a delay adjustment circuitry which incorporates a built-in test circuit. FIG. 2A shows connections between variable delay circuits and the built-in test circuit in the delay adjustment circuitry, and FIG. 2B shows an exemplary configuration of a control signal generator circuitry in the delay adjustment circuitry.
The delay adjustment circuitry shown in FIGS. 2A and 2B includes a pair of variable delay circuits 40 and 41 and a built-in test circuit. The variable delay circuit 40 has an input connected to an input terminal DQOUT0 and an output connected to an output terminal DQ0. Correspondingly, the variable delay circuit 41 has an input connected to an input terminal DQOUT1 and an output connected to an output terminal DQ1. The built-in test circuit includes a test flipflop circuit 61 which outputs an output signal 311 from the output thereof.
The control signal generator circuitry includes mode register sets 71 and 81, control circuits 72 and 82, and inverters 31 to 38.
The control circuit 72 has a set of CAS latency inputs ACL1.5, ACL2.0, ACL2.5, and ACL3.0, and generates drive capability control signals a0 to a3 in response to selection of the CAS latency inputs ACL1.5, ACL2.0, ACL2.5, and ACL3.0. Here, the CAS latency inputs ACL1.5, ACL2.0, ACL2.5 and ACL3.0 are associated with CAS latencies of 1.5, 2.0, 2.5 and 3.0 clock cycles, respectively. The mode register set 71 stores the CAS latency information indicative of the CAS latency to be set for the variable delay circuit 40, and activates selected one of the CAS latency inputs ACL1.5, ACL2.0, ACL2.5, and ACL3.0 of the control circuit 72 in response to the CAS latency information stored therein.
Correspondingly, the control circuit 82 has a set of CAS latency inputs BCL1.5, BCL2.0, BCL2.5, and BCL3.0, and generates drive capability control signals b0 to b3 in response to selection of the CAS latency inputs BCL1.5, BCL2.0, BCL2.5, and BCL3.0. Here, the CAS latency inputs BCL1.5, BCL2.0, BCL2.5 and BCL3.0 are associated with CAS latencies of 1.5, 2.0, 2.5 and 3.0 clock cycles, respectively. The mode register set 81 stores the CAS latency information indicative of the CAS latency to be set for the variable delay circuit 41, and activates selected one of the CAS latency inputs BCL1.5, BCL2.0, BCL2.5, and BCL3.0 of the control circuit 82 in response to the CAS latency information stored therein.
The inverters 31 to 34 receive the drive capability control signals a0 to a3 on the inputs, and generate inverted drive capability control signals ab0 to ab3, respectively, in response to the drive capability control signals a0 to a3. Correspondingly, the inverters 35 to 38 receive the drive capability control signals b0 to b3 on the inputs, and generate inverted drive capability control signals bb0 to bb3, respectively, in response to the drive capability control signals b0 to b3.
The operations of the mode register sets 71, 81 and the control circuits 72 and 82 are identical to those of the mode register set 21 and the control circuit 22 shown in FIG. 1B, respectively.
Referring back to FIG. 2A, the configurations and operations of the variable delay circuits 40 and 41 are identical to those of the variable delay circuit 20. Here, it should be noted that the variable delay circuit 41 uses the drive capability control signals b0 to b3 and inverted drive capability control signals bb0 to bb3, in place of the drive capability control signals a0 to a3 and inverted drive capability control signals ab0 to ab3, respectively.
The output of the variable delay circuit 40 is connected to the data input of the test flipflop 61 through a signal line 201 and the output of the variable delay circuit 41 is connected to the clock input of the test flipflop 61 through a signal line 202. The signal lines 201 and 202 transmit the output signals of the variable delay circuits 40 and 41, respectively. The signal lines 201 and 202 are routed so that the delay of the signal line 201 is identical to that of the signal line 202.
The test flipflop circuit 61 is used to determine the adjusted delay difference between the variable delay circuits 40 and 41. Here, when there is a difference in the delay between the signal lines 201 and 202 due to manufacture variations, for example, the adjusted delay difference determined by the test flipflop circuit 61 includes the difference in the delay between the signal lines 201 and 202. In such a case, the test flipflop circuit 61 cannot determine the adjusted delay difference between the variable delay circuits 40 and 41, accurately.
Let us consider the case where the desired adjusted delay difference between the variable delay circuits 40 and 41 is as small as 10 ps, and there is a delay difference of 20 ps between the signal lines 201 and 202, for example. In this case, the adjusted delay difference is incorrectly determined on the input of the test flipflop circuit 61.
In the following, a description is given of an exemplary operation for failure detection of the delay adjustment circuitry shown in FIGS. 2A and 2B.
The control circuit 72 sets the drive capability control signals a0 to a3 to desired levels under the control of the mode register set 71, and the inverters 31 to 34 set the inverted drive capability control signals ab0 to ab3 to the complementary levels to those of the drive capability control signals a0 to a3. Correspondingly, the control circuit 82 sets the drive capability control signals b0 to b3 to desired levels under the control of the mode register set 81, and the inverters 35 to 38 set the inverted drive capability control signals bb0 to bb3 to the complementary levels to those of the drive capability control signals b0 to b3.
The drive capability control signals a0 to a3, b0 to b3, and the inverted drive capability control signals ab0 to ab3 and bb0 to bb3 are set so that the drive capability of the variable delay circuit 40 are different from that of the variable delay circuit 41.
This is followed by feeding signals to the input terminals DQOUT0 and DQOUT1 at the same time.
As a result, the variable delay circuits 40 and 41 outputs the output signals with delay times controlled by the drive capabilities set thereto. The difference in the drive capability between the variable delay circuits 40 and 41 is observed as the adjusted delay difference.
The test flipflop circuit 61 is triggered by the rising edge of the output signal of the variable delay circuit 41, which is fed to the clock input of the test flipflop circuit 61, to latch the output signal of the variable delay circuit 40, which is fed to the data input of the test flipflop circuit 61. The output signal 311 is outputted from the test flipflop circuit 61 in response to the signal latched by the test flipflop circuit 61.
When the drive capabilities of the variable delay circuits 40 and 41 are successfully controlled in response to the setting values stored in the mode register sets 71 and 81, the adjusted delay difference is observed in the output signals of the adjustment circuits 40 and 41 on the signal lines 201 and 202 as expected.
When there is no failure in the variable delay circuits 40 and 41, the output signals of the variable delay circuits 40 and 41 exhibit an expected adjusted delay difference in accordance with the set values of the drive capability control signals a0 to a3, b0 to b3, and inversed drive capability control signals ab0 to ab3 and bb0 to bb3. It should be noted that, hereinafter, the value of the output signal 311 in the case where the variable delay circuits 40 and 41 operates as desired in response to the drive capability control signals a0 to a3, b0 to b3, and the inverted drive capability control signals ab0 to ab3 and bb0 to bb3 is referred to as the “expected value”. When the actual value of the output signal 311 of the test flipflop circuit 61 is coincident with the expected value, this confirms that the transistors within the variable delay circuits 40 and 41 operate normally.
When there is any failure in the variable delay circuits 40 and 41, on the other hand, the adjusted delay difference between the variable delay circuits 40 and 41 does not match the setting values of the drive capability control signals a0 to a3, b0 to b3, and the inverted drive capability control signals ab0 to ab3 and bb0 to bb3. As a result, the actual value of the output signal 311 outputted by the test flipflop circuit 61 does not match the expected value. This allows detecting the failure in the drive capability adjustment of the transistors within the variable delay circuits 40 and 41.
It should be noted that the inputs of the control circuits 72 and 82 may be controlled by any means other than the mode register sets 71 and 81. For example, the controls of the inputs of the control circuits 72 and 82 may be achieved by the output signals of a counter used for drive ability control, or externally-received signals fed to external test pads.
The failure detection architecture shown in FIGS. 2A and 2B requires eliminating the delay difference between the signal lines 201 and 202 connected between the test flipflop circuit 61 and the variable delay circuits 40 and 41.
One issue is the reduction in the allowed delay adjustment amount due to the enhancement in the operation speed of the system, including a CPU and memories. This may result in that the difference in the delay between the signal lines 201 and 202 caused by interconnection delay variations and/or manufacture variations exceeds the allowed delay adjustment amount. In this case, the difference in the delay caused by interconnection delay variations and/or manufacture variations may be observed as the output signal 311 of the test flipflop circuit 61 in place of the adjusted delay difference between the variable delay circuits 40 and 41. This may cause improper determination of the adjusted delay difference between the variable delay circuits 40 and 41.
This problem may be addressed to some extent, by improving the routing accuracy of the signal lines 201 and 202, which are designed to have the same length, in the circuit layout; however, this approach will face severe difficulty when the allowed adjusted delay difference is significantly reduced down to several pico seconds or less.
Let us consider a case where the adjusted delay difference between the variable delay circuits 40 and 41 is as small as 3 ps, and the delay difference between the signal lines 201 and 202, which is caused by interconnection delay variations and/or manufacture variations, is 6 ps. In this case, the adjusted delay difference between the variable delay circuits 40 and 41 is incorrectly observed on the input terminal of the test flipflop circuit 61 and the test flipflop circuit 61 unsuccessfully determines the adjusted delay difference. In order to address this unsuccessful determination, one approach may be to modify interconnection routing for improving the interconnection delay variations. This approach, however, faces severe difficulty in addressing the delay difference of 6 ps between the signal lines 201 and 202. The test flipflop circuit 61, which observes the adjusted delay difference between the variable delay circuits 40 and 41 influenced by the undesired delay difference exceeding the adjusted delay difference, undesirably outputs an incorrect result as the output signal. This results in that an improper checking of the output signal 311 against the expected value. In other words, the built-in test architecture shown in FIGS. 2A and 2B suffers from a problem that the failure of the variable delay circuits 40 and 41, which provide minute delay adjustments, cannot be detected in the semiconductor integrated circuit.